By R. M. Marston (Auth.)
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Extra resources for 110 Semiconductor Projects for the Home Constructor
In this case, gate off-set biasing is u s e d , so individual c o m p o n e n t a d j u s t m e n t is n o t r e q u i r e d . Voltage gain is a p p r o x i m a t e l y 0 . 9 5 . C is a 2 b o o t s t r a p c a p a c i t o r , a n d increases t h e effective value of gate resistor R b y a b o u t 2 0 t i m e s . C can be o m i t t e d f r o m t h e design, if preferred. 2 MSI s h u n t e d b y 10 p F . With C in place, t h e i n p u t i m p e 2 dance is raised t o a b o u t 4 4 MSI s h u n t e d b y 10 p F .
C. plus a x . signal is a p p l i e d t o Q2 b a s e , a n d t h a t transistor is driven o n . As Q2 is driven o n , its collector m o v e s t o w a r d s +ve line p o t e n t i a l , a n d t h e relay is driven o n . When t h e —ve going p a r t s of t h e i n p u t w a v e f o r m are a p p l i e d t o Ql b a s e , Ql c u t s off, b u t base c u r r e n t c o n t i n u e s t o flow in Q2 via C , so Q2 a n d t h e relay stay o n . c. c. s w i t c h . / ^ p r e v e n t s excessive base c u r r e n t s flowing in Q2.
In s o m e circuits, RB is wired b e t w e e n base 1 a n d g r o u n d , as s h o w n in Fig. 2b either t o c o n t r o l t h e discharge t i m e of C or t o give a +ve o u t p u t pulse during t h e discharge p e r i o d . A —ve pulse is also available across Rs in this p e r i o d , if n e e d e d . S. 75 = 4 . 7 - 9 . 1 kn = 5 MA = 4 mA = T018 58 20 UNIJUNCTION TRANSISTOR PROJECTS N o w t h a t t h e basic principles of t h e u . j . have been described above, we can select a practical unit a n d t h e n go o n t o consider 2 0 or so T0-I8 CASE (BOTTOM VIEW) Fig.
110 Semiconductor Projects for the Home Constructor by R. M. Marston (Auth.)